FIELD OF THE INVENTION
The present invention relates to a decoder connection configuration for memory chips having:
long bit lines running in a first direction; PA1 word lines, which cross the bit lines in a memory cell array and run in a second direction; PA1 word line decoders, which lie in a decoder region and form a first metallization plane, the decoder region adjoining an edge of the memory cell array that runs in the first direction; and PA1 supply lines for the decoder, which are routed in the decoder region in a second metallization plane lying above the first metallization plane, respective plated-through holes being provided between the two metallization planes at lateral edges of the decoder region.
Array segments of integrated semiconductor memories and hence memory cell arrays are intended to be configured as large as possible in order to be able to store as much information as possible in each individual memory cell array. As contiguous array segments become larger, however, row decoders and/or row drivers also become longer, with the result that it becomes increasingly difficult to connect the decoders to power supply networks in a low-impedance manner.
At the present time, row decoders, as indicated in the introduction, are provided parallel to the bit lines at the edge of a memory cell array and, at the same time, are connected to a power supply network via plated-through holes in each case only at their ends. An existing configuration of this type is formed of memory cell array having word lines running in a y-direction and bit lines disposed in an x-direction. A decoder region is provided parallel to the bit lines at the edge of the memory cell array in the x-direction, in which decoder region the individual word lines and their decoders lie extremely close together. A row of power supply lines that are parallel to one another is provided in a second metallization plane above the decoders, which form a first metallization plane, in a manner insulated by a silicon dioxide layer. The power supply lines are electrically connected to the decoders only at the edge of the decoder region via plated-through holes running through the silicon dioxide layer. It is not possible for the plated-through holes to be provided in the course of the power supply lines, for instance in the center thereof, which is due to the fact that, in the metallization plane situated underneath, individual decoders and their word lines lie closely beside one another. Existing decoder connection configurations thus have the plated-through holes only at the edges of the decoder regions that adjoin the memory cell array.
It is a matter of great importance that the individual decoders be connected to the power supply lines with the lowest possible impedance, this currently being effected by the two-sided plated-through hole, at the two ends of the decoder region. Other possibilities consist in implementing the power supply lines as metal tracks that are as wide as possible, or in providing the decoders on both sides of the bit lines.
However, all these measures are associated with a higher area requirement, which is undesirable.